---------------------------------------------------------------------------------- -- Engineer: Roland Leurs -- -- Create Date: 09:07:16 07/27/2014 -- Module Name: AtomIoDecoder - Behavioral -- Project Name: New Atom Main Board - build 2014 -- Target Devices: 9536XL ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity IoDecoder is Port ( Phi2, RW : in STD_LOGIC; HZ2400 : in STD_LOGIC; PC0, PC1 : in STD_LOGIC; Addr : in STD_LOGIC_VECTOR (15 downto 0); AddrLatch : out STD_LOGIC_VECTOR (3 downto 0); CasOut : out STD_LOGIC; oVDG : out STD_LOGIC; oB00X : out STD_LOGIC; oB40X : out STD_LOGIC; oB80X : out STD_LOGIC; oBXXX : out STD_LOGIC; oBFFX : out STD_LOGIC; oIoBusEn : out STD_LOGIC; oVidBusEn : out STD_LOGIC); end IoDecoder; architecture Behavioral of IoDecoder is signal nB00X, nB40X, nB80X, nBDXX, nBFFX, nBXXX, nIoBusEn, nVidBusEn, nVDG: STD_LOGIC; signal pc : STD_LOGIC_VECTOR (2 downto 0); begin process(Addr, Phi2) begin if (Addr(15 downto 13) = "100" or Addr(15 downto 8) = x"BD") and Phi2 = '1' then nVDG <= '0'; else nVDG <= '1'; end if; if Addr(15 downto 4) = "101100000000" then nB00X <= '0'; else nB00X <= '1'; end if; if Addr(15 downto 4) = x"B40" then nB40X <= '0'; else nB40X <= '1'; end if; if Addr(15 downto 4) = x"B80" then nB80X <= '0'; else nB80X <= '1'; end if; if Addr(15 downto 8) = x"BD" then nBDXX <= '0'; else nBDXX <= '1'; end if; if Addr(15 downto 12) = x"B" then nBXXX <= '0'; else nBXXX <= '1'; end if; if Addr(15 downto 4) = x"BFF" then nBFFX <= '0'; else nBFFX <= '1'; end if; if Addr(15 downto 12) /= x"B" or nB00X = '0' or nB40X = '0' or nB80X = '0' or nBDXX = '0' or nBFFX = '0' then nIoBusEn <= '1'; else nIoBusEn <= '0'; end if; if (Addr(15 downto 13) = "100") or (Addr(15 downto 8) = x"BD") then nVidBusEn <= '0'; else nVidBusEn <= '1'; end if; oB00X <= nB00X; oB40X <= nB40X; oB80X <= nB80X; oBXXX <= nBXXX; oBFFX <= nBFFX; oIoBusEn <= nIoBusEn; oVIdBusEn <= nVidBusEn; oVDG <= nVDG; end process; process (Phi2, RW, Addr) begin -- catch A0 ... A3 in latch on write cycle if falling_edge(Phi2) then if RW = '0' and Addr(15 downto 4) = x"B40" then AddrLatch <= Addr(3 downto 0); end if; end if; end process; process (HZ2400, PC0, PC1) begin pc(0) <= PC0; pc(1) <= PC1; pc(2) <= HZ2400; if pc = "001" or pc = "101" or pc = "111" then CasOut <= '0'; else CasOut <= '1'; end if; end process; end Behavioral;