---------------------------------------------------------------------------------- -- Engineer: Roland Leurs -- -- Create Date: 23:09 01/14/2015 -- Module Name: AtomMemoryDecoder - Behavioral -- Project Name: New Atom Main Board - build 2014 -- Target Devices: 9572XL ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity AtomMemoryDecoder is Port ( DD: inout STD_LOGIC_VECTOR (7 downto 0); nBFFX: in STD_LOGIC; RS: in STD_LOGIC; RW: in STD_LOGIC; Phi2: in STD_LOGIC; ClkIn: in STD_LOGIC; Reset: in STD_LOGIC; A15: in STD_LOGIC; A14: in STD_LOGIC; A13: in STD_LOGIC; A12: in STD_LOGIC; ClkOut: out STD_LOGIC; HZ2400: out STD_LOGIC; RA16: out STD_LOGIC; RA15: out STD_LOGIC; RA14: out STD_LOGIC; RA13: out STD_LOGIC; RA12: out STD_LOGIC; nCSRAM: out STD_LOGIC; nCSROM: out STD_LOGIC; nRst: out STD_LOGIC; Rst: out STD_LOGIC; NWDS: out STD_LOGIC; NRDS: out STD_LOGIC; nRAMWE: out STD_LOGIC); end AtomMemoryDecoder; architecture Behavorial of AtomMemoryDecoder is signal count: STD_LOGIC_VECTOR(1 downto 0); signal regBFFE, regBFFF : STD_LOGIC_VECTOR(7 downto 0); signal nWR, nRD, WP : STD_LOGIC; signal OSRAM, BSROM: STD_LOGIC; signal BS0, BS1, BS2: STD_LOGIC; signal XMA0, XMA1: STD_LOGIC; signal ClkSel: STD_LOGIC; type CasCounter is range 0 to 1000; type RstCounter is range 0 to 200000; signal CasClkOut: STD_LOGIC; signal resetFlag: STD_LOGIC; begin process(Phi2) begin -- write BFFE (control register) if falling_edge(Phi2) then if Reset = '0' then regBFFE(3 downto 0) <= x"0"; else if nBFFX = '0' and RS = '0' and RW = '0' then regBFFE <= DD; end if; end if; end if; -- write BFFF (bank switch register) if falling_edge(Phi2) then if Reset = '0' then regBFFF <= x"00"; else if nBFFX = '0' and RS = '1' and RW = '0' then regBFFF <= DD; end if; end if; end if; end process; process (Phi2, RW) begin -- create nRDS signal if Phi2 = '1' and RW = '1' then nRD <= '0'; else nRD <= '1'; end if; -- create nWDS signal if Phi2 = '1' and RW = '0' then nWR <= '0'; else nWR <= '1'; end if; end process; process(ClkIn) variable casClkCnt : casCounter := 0; begin if rising_edge(ClkIn) then -- Clock divider to 1 and 2 MHz clock signals if (ClkSel = '0') then ClkOut <= count(1); else ClkOut <= count(0); end if; count <= STD_LOGIC_VECTOR(unsigned(count) + 1); -- Clock diverder to 2400 Hz clock signal -- If the input clock is not 4MHz then the 831 must be adjusted if casClkCnt = 831 then casClkOut <= not casClkOut; casClkCnt := 0; else casClkCnt := casClkCnt + 1; end if; end if; end process; process (Reset, ClkIn) variable rstClkCnt : rstCounter := 0; begin if rising_edge(ClkIn) then if (Reset = '0') then resetFlag <= '1'; -- reset key has been pressed rstClkCnt := 199999; end if; if resetFlag = '1' then rstClkCnt := rstClkCnt - 1; if (rstClkCnt = 0) then resetFlag <= '0'; end if; end if; end if; end process; process (A15, A14, A13, A12, BS0, BS1, BS2, XMA0, XMA1, OSRAM, WP, RW, Phi2, BSROM) begin -- Address logic in Atom Mode if A15 = '0' and A14 = '1' then RA16 <= '1'; else RA16 <= '0'; end if; if (A15 = '0' and A14 = '1' and A13 = '1') or (A15 = '1' and A14 = '0' and A13 = '1' and A12 = '0') then RA15 <= '1'; else RA15 <= '0'; end if; if (A15 = '0' and A14 = '0') or (A15 = '1' and A14 = '0' and A13 = '1' and A12 = '0' and BS2 = '1') or (A15 = '0' and A14 = '1' and A12 = '1') or (OSRAM = '0' and BSROM = '1') then RA14 <= '1'; else RA14 <= '0'; end if; if (A15 = '1' and A14 = '1' and A13 = '1') or (A15 = '0' and A14 = '0' and A13 = '1') or (A15 = '1' and A14 = '0' and A13 = '1' and A12 = '0' and BS1 = '1') or (A15 = '0' and A14 = '1' and XMA1 = '1') then RA13 <= '1'; else RA13 <= '0'; end if; if (A15 = '1' and A14 = '1' and A12 = '1') or (A15 = '0' and A14 = '0' and A12 = '1') or (A15 = '1' and A14 = '0' and A13 = '1' and A12 = '0' and BS0 = '1') or (A15 = '0' and A14 = '1' and XMA0 = '1') then RA12 <= '1'; else RA12 <= '0'; end if; if (A15 = '1' and A14 = '1' and OSRAM = '1') or (A15 = '0') or (A15 = '1' and A14 = '0' and A13 = '1' and A12 = '0') then nCSRAM <= '0'; else nCSRAM <= '1'; end if; if (A15 = '1' and A14 = '1' and OSRAM = '0') then nCSROM <= '0'; else nCSROM <= '1'; end if; if (A15 = '0' and RW = '0' and Phi2 = '1') or (A15 = '1' and A14 = '1' and WP = '0' and RW = '0' and Phi2 = '1') or (A15 = '1' and A14 = '0' and A13 = '1' and A12 = '0' and WP = '0' and RW = '0' and Phi2 = '1') then nRAMWE <= '0'; else nRAMWE <= '1'; end if; end process; -- Signals to output NRDS <= nRD; NWDS <= nWR; Rst <= not resetFlag; nRst <= resetFlag; HZ2400 <= casClkOut; BS0 <= regBFFF(0); BS1 <= regBFFF(1); BS2 <= regBFFF(2); XMA0 <= regBFFE(0); XMA1 <= regBFFE(1); OSRAM <= regBFFE(2); BSROM <= regBFFE(3); ClkSel <= regBFFE(6); WP <= regBFFE(7); -- read registers DD <= regBFFE when (nBFFX = '0' and RW = '1' and RS = '0') else regBFFF when (nBFFX = '0' and RW = '1' and RS = '1') else (others => 'Z'); end Behavorial;